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n1506 ms pc b8-4581 no.6206-1/17 any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein. LA7137M overview the LA7137M is a video output interface ic for dvd players an d is optimal as the driver ic for dvd players that provide composite signal/s signal, component signal, and rgb signal video outputs. since this ic integrates a y/c mixer on the same chip, the d/a converter composite output can be omitted. the LA7137M also integrates s1 and s2 dc voltage and d/a converter reference voltage generation on chip, allowing most components other than the drivers to be omitted. functions ? clamps ? y/c mixer ? amplifier ? s1 and s2 dc output ? 75 ? driver ? d/a converter reference voltage output features ? video signal-to-noise ratio : -80db ? frequency characteristics : flat to 10mhz ? y/c time difference : less than 2ns ? signal dynamic range : 170ire. ? can support all major signal types : composite/s signals, component signals, and baseband (rgb) signals. furthermore, the ic input type can be switched by the system mi crocontroller (since the input capacitors are shared). ? two 75 ? driver systems that can be independently muted by the system microcontroller. ? the clamp pulses required for component signal input are generated internally in the ic. ? either of two amplifier gain levels, 8.5 and 6db, can be selected. ? a built-in regulator circuit provides a stable dc voltage output that is independent of v cc fluctuations. specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 10.0 v allowable power dissipation pd max ta 75 c * mounted on a board 525 mw operating temperature topr -20 to +75 c storage temperature tstg -40 to +150 c * only when mounted on a 114.376.11.6mm 3 glass epoxy board monolithic linear ic dvd analog video output i/f ic orderin g numbe r : en6206
LA7137M no.6206-2/17 operating conditions at ta = 25 c parameter symbol conditions ratings unit recommended supply voltage v cc 8.0 v operating supply voltage range v cc op 7.6 to 8.4 v electrical characteristics at ta = 25 c, v cc = 7.6 to 8.4v ratings parameter symbol input signal test point conditions min typ max unit current drain 1 i cc 1 video system current drain 14.3 17.9 21.5 ma current drain 2 i cc 2 75 ? driver current drain ; no signal 14.4 18.0 21.6 ma (a) for a pin 10 (y signal) input when composite/s selected amplifier gain (low) g y m sig.1 t13/15 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db amplifier gain (high) g y h sig.1 t13/15 the gain for a 761mvp- p 100khz signal 7.38 7.6 7.81 db clamp voltage c 10 h sig.1 t10 the t10 sync tip potential for a 761mvp-p input 3.85 4.20 4.55 v (b) for a pin 6 (chrominance signal) input when composite/s selected amplifier gain (low) g c m sig.2 t17/19 the gain for a 711mvp- p 3.58mhz signal 5.05 5.27 5.48 db amplifier gain (high) g c h sig.2 t17/19 the gain for a 544mvp- p 3.58mhz signal 7.38 7.6 7.81 db chrominance signal input dc voltage d 6 h sig.2 t6 the t6 offset voltage for a 544mvp-p input 4.4 4.75 5.1 v (c) for a pin 3 (composite signal) input when composite selected amplifier gain (low) g s m1 sig.3 t21/23 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db amplifier gain (high) g s h1 sig.3 t21/23 the gain for a 761mv p-p 100khz signal 7.38 7.6 7.81 db clamp voltage c 3 h sig.3 t3 the t3 sync tip potential for a 761mvp-p input 4.0 4.35 4.7 v (d) for a pins 6 and 10 (s signal) input when s is selected amplifier gain (low) g s m2 sig.1 sig.2 t21/23 the gain for a 996mvp-p 100khz signal or a 711mvpp 3.58khz signal 4.92 5.27 5.61 db amplifier gain (high) g s h2 sig.1 sig.2 t21/23 the gain for a 761mvp-p 100khz signal or a 544mvpp 3.58khz signal 7.25 7.6 7.94 db (e) the gain ratios between the differen t signals when composite is selected y/chrominance amplifier gain ratio ? y c sig.1 sig.2 t13/15 t17/19 the ratio of the g y h gain for (a) and the g c h gain for (b) -3 0 3 % y/composite amplifier gain ratio ? y s 1 sig.1 sig.3 t13/15 t21/23 the ratio of the g y h gain for (a) and the g s h1 gain for (c) -3 0 3 % chrominance/composite amplifier gain ratio ? c s 1 sig.2 sig.3 t17/19 t21/23 the ratio of the g c h gain for (b) and the g s h1 gain for (c) -3 0 3 % (f) the gain ratios between the different signals when s is selected y/s amplifier gain ratio ? y s 2 sig.1 sig.2 t13/15 t21/23 the ratio of the g y h gain for (a) and the g s h2 gain for (d) -4.5 0 4.5 % chrominance/s amplifier gain ratio ? c s 2 sig.1 sig.2 t17/19 t21/23 the ratio of the g c h gain for (b) and the g s h2 gain for (d) -4.5 0 4.5 % (g) the pin 10 (y signal) input when component is selected amplifier gain (low) g y m sig.1 t13/15 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db amplifier gain (high) g y h sig.1 t13/15 the gain for a 761mvp- p 100khz signal 7.38 7.6 7.81 db y input clamp voltage c 10 h sig.1 t10 the t10 sync tip potential for a 761mvp-p input 3.85 4.20 4.55 v (h) the pin 6 (b-y or r-y signal) input when component is selected amplifier gain (low) g n m sig.4 t17/19 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db amplifier gain (high) g n h sig.4 t17/19 the gain for a 761mvp- p 100khz signal 7.38 7.6 7.81 db input pedestal clamp voltage p 6 h sig.4 t6 the t6 pedestal potential for a 761 mvp-p input 4.4 4.75 5.1 v amplifier gain (low) g n m sig.4 t21/23 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db continued on next page.
LA7137M no.6206-3/17 continued from preceding page. ratings parameter symbol input signal test point conditions min typ max unit (i) the pin 3 (b-y or r-y signal) input when component is selected amplifier gain (high) g n h sig.4 t21/23 the gain for a 761mvp- p 100khz signal 7.38 7.6 7.81 db input pedestal clamp voltage p 3 h sig.4 t3 the t3 pedestal potential for a 761 mvp-p input 4.4 4.75 5.1 v (j) the gain ratios between the differen t signals when component is selected y/component amplifier gain ratio 1 ? y1 sig.1 sig.4 t13/15 t17/19 the ratio of the g y h gain for (e) and the g n h gain for (f) -3 0 3 % y/component amplifier gain ratio 2 ? y2 sig.1 sig.4 t13/15 t21/23 the ratio of the g y h gain for (e) and the g n h gain for (g) -3 0 3 % component amplifier gain ratio ? n sig.4 sig.4 t17/19 t21/23 the ratio of the g n h gain for (f) and the g n h gain for (g) -3 0 3 % (k) the pin 10 (rgb signal) input when baseband is selected amplifier gain (low) g b m sig.1 t13/15 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db amplifier gain (high) g b h sig.1 t13/15 the gain for a 761mvp- p 100khz signal 7.38 7.6 7.81 db input clamp voltage c 10 h sig.1 t10 the t10 sync tip potential for a 761mvp-p input 3.85 4.20 4.55 v (l) the pin 6 (rgb signal) input when baseband is selected amplifier gain (low) g b m sig.1 t13/15 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db amplifier gain (high) g b h sig.1 t13/15 the gain for a 761mvp- p 100khz signal 7.38 7.6 7.81 db input clamp voltage c 6 h sig.1 t10 the t10 sync tip potential for a 761mvp-p input 4.0 4.35 4.7 v (m) the pin 3 (rgb signal) input when baseband is selected amplifier gain (low) g b m sig.1 t13/15 the gain for a 996mvp- p 100khz signal 5.05 5.27 5.48 db amplifier gain (high) g b h sig.1 t13/15 the gain for a 761mvp- p 100khz signal 7.38 7.6 7.81 db input clamp voltage c 3 h sig.1 t10 the t10 sync tip potential for a 761mvp-p input 4.0 4.35 4.7 v (n) the gain ratios between the different signals when baseband is selected baseband amplifier gain ratio 1 ? b1 sig.1 sig.1 t13/15 t17/19 the ratio of the g b h gain for (i) and the g b h gain for (j) -3 0 3 % baseband amplifier gain ratio 2 ? b2 sig.1 sig.1 t13/15 t21/23 the ratio of the g b h gain for (i) and the g b h gain for (k) -3 0 3 % baseband amplifier gain ratio 3 ? b3 sig.1 sig.1 t17/19 t21/23 the ratio of the g b h gain for (j) and the g b h gain for (k) -3 0 3 % (o) gain frequency characteristics (common to all modes and input signals other than y/c mixed mode) 6mhz low-pass filter attenuation f y 6 sig.1 t13/15 the difference between g y h and the gain for a 761mvp-p, 6mhz input -0.5 0 +0.5 db 10mhz low-pass filter attenuation f y 10 sig.1 t13/15 the difference between g y h and the gain for a 761mvp-p, 10mhz input -0.5 0 +0.5 db (p) dc voltage when output muting applied (common to all modes) pin 13 voltage v 13 t13 3.7 4.05 4.4 v pin 15 voltage v 15 t15 3.7 4.05 4.4 v pin 17 voltage v 17 t17 3.9 4.25 4.6 v pin 19 voltage v 19 t19 3.9 4.25 4.6 v pin 21 voltage v 21 t21 3.9 4.25 4.6 v pin 23 voltage v 23 t23 3.9 4.25 4.6 v (q) output dc voltage characteristics d/a converter reference voltage v da t12 when driving an 800a load current 3.2 3.4 3.6 v 4 : 3 output mode dc v 43 t16 in 4 : 3 control mode (no load) 0 0.01 0.35 v letterbox output dc v lb t16 in letterbox control mode (when driving a 500 a load current) 2.05 2.2 2.35 v squeezed output dc v sq t16 in squeeze control mode (when driving a 500 a load current) 4.4 4.7 5.0 v note : the amplifier gain and amplifier gain ratios are the va lues when the components shown in the test circuit diagram are al l connected.
LA7137M no.6206-4/17 switching characteristics ("-" indicates ok under all conditions) control voltage (unit: v) switching conditions symbol vdc1 vdc2 vdc4 vdc5 vdc11 vdc22 sw1 sw2 i cc 1 0 0 3.3 0 3.3 3.3 on on i cc 2 0 0 3.3 0 3.3 3.3 on on (a) for a pin 10 (y signal) input when composite/s selected g y m 0/3.3 0 - - 0 3.3 on/off on g y h 0/3.3 0 - - 3.3 3.3 on/off on c 10 h 0/3.3 0 - - 3.3 3.3 on/off on (b) for a pin 6 (chrominance signal) input when composite/s selected g c m 0/3.3 0 - - 0 3.3 on/off on g c h 0/3.3 0 - - 3.3 3.3 on/off on c 6 h 0/3.3 0 - - 3.3 3.3 on/off on (c) for a pin 3 (composite signal) input when composite selected g s m1 0/3.3 0 - - 0 3.3 on/off on g s h1 0/3.3 0 - - 3.3 3.3 on/off on c 3 h 0/3.3 0 - - 3.3 3.3 on/off on (d) for a pins 3 (s signal) input when s is selected g s m2 0/3.3 0 - - 0 3.3 on/off on g s h2 0/3.3 0 - - 3.3 3.3 on/off on (e) the gain ratios between the differen t signals when composite is selected ? y c 0/3.3 0 - - 3.3 3.3 on/off on ? y s 1 0/3.3 0 - - 3.3 3.3 on/off on ? c s 1 0/3.3 0 - - 3.3 3.3 on/off on (f) the gain ratios between the different signals when s is selected ? y s 2 0/3.3 0 - - 3.3 0 on/off on ? c s 2 0/3.3 0 - - 3.3 0 on/off on (g) the pin 10 (y signal) input when component is selected g y m 0/3.3 3.3 - - 0 3.3 on/off on g y h 0/3.3 3.3 - - 3.3 3.3 on/off on c 10 h 0/3.3 3.3 - - 3.3 3.3 on/off on (h) the pin 6 (b-y or r-y signal) input when component is selected g n m 0/3.3 3.3 - - 0 3.3 on/off on g n h 0/3.3 3.3 - - 3.3 3.3 on/off on p 6 h 0/3.3 3.3 - - 3.3 3.3 on/off on (i) the pin 3 (b-y or r-y signal) input when component is selected g n m 0/3.3 3.3 - - 0 3.3 on/off on g n h 0/3.3 3.3 - - 3.3 3.3 on/off on p 3 h 0/3.3 3.3 - - 3.3 3.3 on/off on (j) the gain ratios between the differen t signals when component is selected ? y1 0/3.3 3.3 - - 3.3 3.3 on/off on ? y2 0/3.3 3.3 - - 3.3 3.3 on/off on ? n 0/3.3 3.3 - - 3.3 3.3 on/off on (k) the pin 10 (rgb signal) input when baseband is selected g b m 0/3.3 - - - 0 3.3 on/off off g b h 0/3.3 - - - 3.3 3.3 on/off off c 10 h 0/3.3 - - - 3.3 3.3 on/off off (l) the pin 6 (rgb signal) input when baseband is selected g b m 0/3.3 - - - 0 3.3 on/off off g b h 0/3.3 - - - 3.3 3.3 on/off off c 6 h 0/3.3 - - - 3.3 3.3 on/off off (m) the pin 3 (rgb signal) input when baseband is selected g b m 0/3.3 - - - 0 3.3 on/off off g b h 0/3.3 - - - 3.3 3.3 on/off off c 3 h 0/3.3 - - - 3.3 3.3 on/off off continued on next page.
LA7137M no.6206-5/17 continued from preceding page. control voltage (unit: v) switching conditions symbol vdc1 vdc2 vdc4 vdc5 vdc11 vdc22 sw1 sw2 (n) the gain ratios between the different signals when baseband is selected ? b1 0/3.3 - - - 3.3 3.3 on/off off ? b2 0/3.3 - - - 3.3 3.3 on/off off ? b3 0/3.3 - - - 3.3 3.3 on/off off (o) gain frequency characteristics (common to all modes and input signals other than y/c mixed mode) f y 6 0/3.3 0 - - 3.3 3.3 on/off on f y 10 0/3.3 0 - - 3.3 3.3 on/off on (p) dc voltage when output muting applied (common to all modes) v 13 0 - - - 0/3.3 0/3.3 on - v 15 3.3 - - - 0/3.3 0/3.3 on - v 17 0 - - - 0/3.3 0/3.3 on - v 19 3.3 - - - 0/3.3 0/3.3 on - v 21 0 - - - 0/3.3 0/3.3 on - v 23 3.3 - - - 0/3.3 0/3.3 on - (q) output dc voltage characteristics v da - - - - 0/3.3 0/3.3 - - v 43 - - 0 0 0/3.3 0/3.3 - - v lb - - 0 3.3 0/3.3 0/3.3 - - v sq - - 3.3 0 0/3.3 0/3.3 - - control pin functions pin no. pin state low open high pin voltage 0 to 0.6v 1.55 to 1.75v 2.7 to 5v 1 75 ? driver muting 13, 17, 21 muted not muted 15, 19, 23 muted pin voltage 0 to 0.6v 1.55 to 1.75v 2.7 to 5v 2 signal input type switching composite/ s mode baseband mode component mode pin voltage 0 to 1v 2.7 to 8v (note) 11 amplifier gain switching 6db 8.5db pin voltage 0 to 1v 2.7 to 8v (note) 22 y/c mixer control y/c mi xed mode composite mode note : never apply a voltage higher than the v cc voltage at pins 9 and 20 to pin 11 or pin 22. * : y/c mixed mode is illegal in modes other than composite/s mode. * : in composite mode, use pin 6 to input the chrominance signal capacitor-coupled, pin 3 for the clamped composite signal, and pin 10 for the clamped y signal. however, in s mode, pin 3 will have no input. in component mode, pins 3 and 6 will be pedestal clampe d b-y and r-y signals, respectively, while pin 10 will be the clamped y signal input. in baseband mode, pins 3, 6, and 10 are all clamped inputs, for the rgb signals, respectively. pins 11 and 22 must never be left open. pin 4 pin 5 pin 16 output dc 0 to 1v 0 to 1v low (0v) 4 : 3 mode 0 to 1v 2.6 to 5v middle (2.5v) letterbox mode 2.6 to 5v 0 to 1v high (5v) squeezed mode 2.6 to 5v 2.6 to 5v illegal values
LA7137M no.6206-6/17 design guaranteed items (at ta = 25c) ratings parameter symbol conditions min typ max unit inter-channel crosstalk ct input an f = 4mhz signal to another channel such that the capacitor-coupled output becomes 1vp-p. measure the amplitude of the 4mhz component on the monitored channel. this parameter is stipulated to be the ratio of that level with the amplitude of the 4mhz component on that other channel. -65 -60 db video signal-to-noise ratio sn input a white 100% signal and apply a 3.3v level to pin 11. measure the signal-to-noise ratio in the output signal. -80 -78 db differential gain dg input a standard 1vp-p staircase signal (color) and leave pin 11 open. measure the differential gain in the output signal. note that the components shown in the test circuit diagram for this parameter must be inserted at this time. 0.5 2 % differential phase dp input a standard 1vp- p staircase signal (color) and leave pin 11 open. measure the differential phase in the output signal. note that the components shown in the test circuit diagram for this parameter must be inserted at this time. -1 0 1 db inter-channel crosstalk ct input an f = 4mhz signal to another channel such that the capacitor-coupled output becomes 1vp-p. measure the amplitude of the 4mhz component on the monitored channel. this parameter is stipulated to be the ratio of that level with the amplitude of the 4mhz component on that other channel. -65 -60 db video signal-to-noise ratio sn input a white 100% signal and apply a 3.3v level to pin 11. measure the signal-to-noise ratio in the output signal. -74 -72 db differential gain dg input a standard 761mvp-p staircase signal (color) and apply a 3.3v level to pin 11. measure the differential gain in the output signal. note that the components shown in the test circuit diagram for this parameter must be inserted at this time. 4 5.5 % differential phase dp input a standard 761mvp-p staircase signal (color) and apply a 3.3v level to pin 11. measure the differential gain in the output signal. note that the components shown in the test circuit diagram for this parameter must be inserted at this time. -1 0.5 1.5 db package dimensions unit : mm (typ) 3112b sanyo : mfp24s(300mil) 1 12 13 24 12.5 0.63 7.6 5.4 0.15 1.0 0.35 (0.75) 1.7max 0.1 (1.5)
LA7137M no.6206-7/17 block diagram 1 mute-sw signal-in.sw composite.in squeeze.sw letter-box.sw c-in gnd1 + reg v cc 1 y.in amp.sw dac-dc.out 2 3 4 5 6 7 8 9 10 11 12 24 gnd2a composite.out2 composite-s.sw composite.out1 v cc 2 c.out2 gnd2b c.out1 c-dc.out y.out2 gnd2c y.out1 23 22 21 20 19 18 17 16 15 14 13 pedestal clamp clamp pedestal clamp clamp reg to pedestal clamp clamp v ref 2step amp 75 ? driver c offset dc ctl 2step amp 2step amp sync sep y c mix 75 ? driver 75 ? driver 75 ? driver 75 ? driver 75 ? driver ctl + + + + + +
LA7137M no.6206-8/17 pin functions for more information on the pin functions, see the i/o circuit diagrams, and for an operating description, see the block diagram. note that the data shown below consists of typical values and that detailed ratings are provided in the electrical characteristics. pin no. pin i/o pin voltage i/o impedance description equivalent circuit 10 y-in i 4.2v clamp form input pin for either the y or a baseband signal. this pin is used for the y signal for composite/s and component signal input, and for one of the rgb signals with sync. keyed clamping (clamping at the lowest point in the signal, that is, at the sync tip) is applied whichever signal is input. if a component sign al is input, sync separation is performed and a clamp pulse for pedestal clamping is produced. the clamped signal is amplified by an amplifier that can be switched between two levels so that it becomes 2vp-p with an output amplitude of 140ire. 13 y.out1 o 2.7v 11.6 ? 75 ? driver output for the signal input to pin 10. the pin 10 output signal is split into two, and one is passed through a muting circuit that mutes when pin 1 is low (0v) and output to the 75 ? driver. 15 y.out2 o 2.7v 11.6 ? 75 ? driver output for the signal input to pin 10. of the pin 10 input signals, the other signal is passed through a muting circuit that mutes when pin 1 is high (3.3 to 5.0v) and output to the 75 ? driver. 6 c-in i 4.8v 10k ? input pin for chrominance, component, and baseband signals. the chrominance signal must be input to this pin when a composite/s signal input is used. the signal must be capacitor coupled. the b-y or r-y signal must be input to this pin when a component signal is input. the signal is clamped at the pedestal level. any one of the rgb with sync signals must be input to this pin when a baseband signal is input. keyed clamping will be applied to the signal. the capacitor coupled or clamped signal is amplified by an amplifier that can be switched between two levels so that it becomes 2vp-p with an output amplitude of 140ire. continued on next page. in v cc v cc v cc v cc 200 ? 100k ? 19k ? 50 a out v cc v cc 50 ? out v cc v cc 50 ? in v cc v cc v cc v cc v cc 200 ? 10k ? 200 ? 100k ? 19k ? 19k ? 200 a 3 a 100 a v cc 100 a clamp pulse
LA7137M no.6206-9/17 continued from preceding page. pin no. pin i/o pin voltage i/o impedance description equivalent circuit 17 c.out1 o 3.9v 11.6k ? 75 ? driver output for the signal input to pin 6. the pin 6 output signal is split into two, and one is passed through a muting circuit that mutes when pin 1 is low (0v) and output to the 75 ? driver. 19 c.out2 o 3.9v 11.6k ? 75 ? driver output for the signal input to pin 6. of the pin 10 input signals, the other signal is passed through a muting circuit that mutes when pin 1 is high (3.3 to 5.0v) and output to the 75 ? driver. 3 composite.in i 4.5v clamp form input pin for composite, component, and baseband signals. if a composite signal is input, it must be input to this pin, and if a baseband signal is input, any one of the rgb with sync signals must be input to this pin. keyed clamping will be applied to the signal. for s signal input, this pin must be dropped to ground. for component signal input, input either the b-y or r-y signal to this pin. the signal will be clamped at the pedestal level. the clamped signal is amplified by an amplifier that can be switched between two levels so that it becomes 2vp-p with an output amplitude of 140ire. 21 composite. out1 o 3.57v 11.6 ? 75 ? driver output for the signal input to pin 3. the pin 3 output signal is split into two, and one is passed through a muting circuit that mutes when pin 1 is low (0v) and output to the 75 ? driver. continued on next page. out v cc v cc 50 ? out v cc v cc 50 ? in v cc v cc v cc v cc v cc 200 ? 200 ? 100k ? 19k ? 19k ? 200 ? 100 a 2 a 100 a clamp pulse out v cc v cc 50 ?
LA7137M no.6206-10/17 continued from preceding page. pin no. pin i/o pin voltage i/o impedance description equivalent circuit 23 composite. out2 o 3.57v 11.6 ? 75 ? driver output for the signal input to pin 3. of the pin 3 input signals, the other signal is passed through a muting circuit that mutes when pin 1 is high (3.3 to 5.0v) and output to the 75 ? driver. 1 mute-sw i 1.7v 21k ? controls the muting applied to the output signals. this pin can be controlled from a 3.3 to 5v power supply microcontroller. (see the control pin function table.) 2 signal-in.sw i 1.7v 21k ? switches the input circuit types of pins 3 and 6 to match the type of the input signal. this pin can be controlled from a 3.3 to 5v power supply microcontroller. (see the control pin function table.) 4 squeeze.sw i 2.40v 9.0g ? inputs squeeze control information from the system microcontroller. this pin can be controlled from a 3.3 to 5v power supply microcontroller. (see the control pin function table.) 5 letter-box.sw i 2.43v 8.1g ? inputs letterbox control information from the system microcontroller. this pin can be controlled from a 3.3 to 5v power supply microcontroller. (see the control pin function table.) continued on next page. out v cc v cc 50 ? in 1k ? 33k ? 52k ? 200 a 4.25v v cc in 1k ? 33k ? 52k ? 200 a 4.25v v cc in 5k ? 50 a v cc in 5k ? 100 a v cc
LA7137M no.6206-11/17 continued from preceding page. pin no. pin i/o pin voltage i/o impedance description equivalent circuit 16 c-dc.out o 4.7v 4.1 ? the LA7137M creates, and outputs from this pin, a stabilized dc voltage based on the control information input to pins 4 and 5. this pin outputs a low level (0v) for 4 : 3 mode, a middle level (2.2v) for letterbox mode, and a high level (5v) for squeeze mode. a 10k ? resistor must be inserted to superimpose the dc voltage output from pin 17 on the capacitor coupled chrominance output. (see the application circuit diagram.) 11 amp-sw i 2.4v 9.0g ? control pin that sw itches the amplifier gain to match the amplitude of the input signal. this pin's input level can be switched between v cc and ground on the printed circuit board even by a 3.3 to 5.0v power supply microcontroller. (see the control pin functions table.) 22 composite- s.sw p 2.4v 9.0g ? controls the on/off state of the y/c mixer. when using a d/a converter that omits the composite output, the y/c mixer must be turned on. at the same time as mixing the y signal input to pin 10 with the chrominance signal input to pin 6, pin 3 will be dropped to ground. when pin 2 control specifies a signal type other than composite/s signal, this pin must be tied high. this pin's input level can be switched between v cc and ground on the printed circuit board even by a 3.3 to 5.0v power supply microcontroller. (see the control pin functions table.) 12 dac-dc.out o 3.4v 4.0 ? outputs a dc reference voltage for use by a d/a converter. in particular, it outputs a 3.3v level. this reference voltage is unaffected by v cc fluctuations or temperature and can be used in conjunction with a resistor divider to produce the dc level required by the d/a converter. 7 gnd1 p 0v ground for systems other than the 75 ? driver system. continued on next page. 150 a 50 a out v cc v cc v cc 200 ? 50k ? 200 ? in 5k ? 300 a v cc in 5k ? 100 a v cc 200 a 50 a out v cc v cc v cc 200 ? 200 ?
LA7137M no.6206-12/17 continued from preceding page. pin no. pin i/o pin voltage i/o impedance description equivalent circuit 8 reg o 4.35v 1.5k ? external pin for the regulator circuit that creates the ic internal reference voltage. since the ic internal noise is influenced by the stability of this regulator, we recommend connecting a 470 f capacitor to this pin to if assuring a -80db signal-to-noise ratio is required. 9 v cc 1 p 8v v cc (8v applied) for systems other than the 75 ? driver system. insert a 47 f capacitor between this pin and pin 7. 20 v cc 2 p 8v v cc (8v applied) for the 75 ? driver system. insert a 47 f capacitor between this pin and pin 14, 18, or 24. the pcb layout related to this pin requires care due to the large amplitude output signals handled. 14 gnd2c p 0v ground for the 75 ? driver system (pin 13 or 15). the pcb layout related to this pin requires care due to the large amplitude output signals handled. 18 gnd2b p 0v ground for the 75 ? driver system (pin 17 or 19). the pcb layout related to this pin requires care due to the large amplitude output signals handled. 24 gnd2a p 0v ground for the 75 ? driver system (pin 21 or 23). the pcb layout related to this pin requires care due to the large amplitude output signals handled. out v cc v cc 15k ? 10k ? 29.2k ? 12k ? 11k ? 10pf m 10k ?
LA7137M no.6206-13/17 sample application circuit single composite/s signal plus single component signal application using a single d/a converter application circuit diagram for end pr oduct that provides one output system each for composite/s and component outputs and the d/a converter output pin is shared between the s signal and the component signal systems. the muting control can be used to switch between the composite/s and component outputs. the system microcontroller must be programmed to turn the y/c mixer off when the component signal system is used. 1 mute-sw 24 gnd2a 2 signal-in.sw 23 composite.out2 3 composite.in 22 composit-s.sw 4 squeeze.sw 21 composite.out1 5 letter-box.sw 20 v cc 2 6 c-in 19 c.out2 7 gnd1 18 gnd2b 8 reg 17 c.out1 9v cc 1 16 c-dc.out 10 y.in 15 y.out2 11 amp.sw 14 gnd2c 12 dac-dc.out 13 y.out1 LA7137M microcontroller 0.1 f 0.1 f 0.1 f yc/mix-ctl-out mute-ctl-out signal-ctl-out s2-ctl-out s1-ctl-out dac component-out1 chroma-out component-out2 y-out1 y-out2 reference-dc-in v cc 8v 62 ? 470 f 62 ? 470 f 62 ? 10k ? 470 f 62 ? 470 f 62 ? 470 f 62 ? 470 f 100 h 47 f 47 f 0.01 f 0.01 f 470 f 100 h component-out composite-out y c y s-out + + + + + + + + +
LA7137M no.6206-14/17 dvd video player system block diagram pickup spindle motor drivers lb11995/m actuator drivers la6543/m head amplifiers la9700m la9701m dvd decoder 1m to 16m dram av i/f mpu lc87f (8 bits) lc62f (16 bits) d/a sdram d/a lcd key audio dec-out audio out * lc897240 * ; planning LA7137M video out digital servo lc78650ne lc78651w *lc78652w cd decoder auddio decoder mpeg2 decoder video driver
LA7137M no.6206-15/17 test circuit 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 mute-sw top view gnd2a signal-in.sw composite.out2 composite.in composit-s.sw squeeze.sw composite.out1 letter-box.sw v cc 2 c-in c.out2 gnd1 gnd2b reg c.out1 v cc 1 c-dc.out y.in y.out2 amp.sw gnd2c dac-dc.out y.out1 LA7137M on off sw1 vdc1 0.6/2.7v vdc2 0.6/2.7v vdc4 1/2.6v vdc5 1/2.6v vdc11 1/2.7v vdc9 8v on t3 c3 c6 0.1 f 0.1 f off sw2 vin3 vin6 vin10 i12 800 a t6 c10 0.1 f t10 c8 470 f t8 t12 i16 500 a vdc20 8v vdc22 1/2.7v r13 c13 62 ? r13a 75 ? 470 f r15 c15 62 ? r15a 75 ? 470 f r17 c17 62 ? r17a 75 ? 470 f r19 c19 62 ? r19a 75 ? 470 f r21 c21 62 ? r21a 75 ? 470 f t23 t23a t21 t21a t19 t19a t17 t16 t17a t15 t15a t13 t13a r23 c23 62 ? r23a 75 ? 470 f ++++++ + + + +
LA7137M no.6206-16/17 input signal for test p-p sin wave 1h 40ire sig.1 140ire sin wave 1h sig.4 70ire p-p sin wave 1h 40ire sig.3 140ire p-p 140ire p-p 100ire sin wave 1h sig.2
LA7137M ps no.6206-17/17 specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of november, 2006. specifications and inform ation herein are subject to change without notice.

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